In General, a number of times and Bus specifications, and is expanding all the time between mainframe computers and the interface device, data transfer speed, capacity, and quality of the application process. Here we profile several important bus specifications. （1）PCI（Peripheral Component Interconnect） 1992, Intel launched the PCIv1.0 Bus (Peripheral Component Interconnect) opening the mainstream PCI series Bus of age. Belonging to PCI local bus (local bus) which PCI series include: (A) beginning to support the 32bits/33MHz, PCI Bus for transmission speeds of up to 1Gbps. (B) in 1995, PCI v2.0/v2.1, designed for Pentium64-bit addressing, 3.3V, low voltage and plug-and-play (Plug-and Play;PnP) features per second maximum data transfer speed of 264MB. (C) 1999 PCI v2.2, Low Profile PCI, PCI-x, Mini-PCI etc, widely used in all kinds of platforms, Laptop, Desktop, Server, and industrial systems, as the internal data bus to PCI, external interface devices online using USB, Firewire, PCMCIA, Cardbus or Expresscard. Insert the PCI and PCI-x hot (Hot Plugging), is to let the Server without disrupting the operational conditions for maintenance service key. (D) also have to meet the Server data capacity, based on the PCI 2.2, increasing power management and hot-insertion technology and speeds up to 8.5Gbps (1GB/s,64bits/133MHz) PCI-X1.0;2002 launched the highest transmission speed of up to 34Gbps (4.2GB/s,64bits/533MHz), PCI-X2.0, and so on. PCI can interface device directly to the computer's central processing unit, and upgrade the data transfer speed of microprocessors and interfacing between devices, that is, point to download (Multi-Drop) parallel bus technology. PCI architecture including a bridge, as the CPU and PCI local bus local bus, and anchor between the system memory bus. Because outside of PCI is independent of the CPU, so when you replace or upgrade the CPU, does not affect the interface device, you don't have to redesign of the Bus. （2）AGP（Accelerated Graphics Port） If the audio and video multimedia data transmission, such as drawing, fine quality guaranteed quality level of clarity and resolve alone PCI may be stretched. In 1997 made by the Intel data width is 32 bits, frequency of 66 MHz AGP v1.0 specification, and now to introduce transfer rates of up to 2.1GB/s (32bits/533MHz) AGP 8X, is designed specifically for graphics cards and display adapters, belongs to the exclusive bus between the microprocessor and graphics chip. AGP is an effective high speed transfers to/from image information between the microprocessor and graphics chip, mainly in response to increasingly complex 3D games and application of higher order software, need a lot of texture (texture mapping) transmission needs. Board supports AGP, Visual signals to the computer through the AGP exclusive channel for the round trip between the microprocessor and graphics chip, you don't have to share with other signals PCI transmission speed speed up naturally, which, like the image data transfer on the AGP bus lanes, no need for other PCI lanes choked with other information on the mutex. With the popularity of multimedia applications, AGP has become a basic design for Desktop or Laptop. Users in addition to using the AGP slot to install the display adapter, more quickly send the data to a microprocessor, also uses Unified Memory Architecture (UMA) technology serves as the main storage memory use, and reduce the display of high memory requirements, this is a regular session player alternative of prudent spending. （3）PCI Express As many high-speed transmission and wireless communications interface equipment of appears, traditional PCI schema has cannot meet such as Fiber Channel, and Gigabit Ethernet, and Serial ATA, and Graphics, of multimedia application; also, attached received interface equipment more more, PCI Bus for adaptation many different type State of interface equipment transmission interface, on will produced more of noise, this will makes shadow audio, clutter not Qing and reduced Bus transmission data of quality. Therefore, host manufacturers and Bus parts and components manufacturers look forward to a general-purpose interface Bus standards to meet different market needs and in terms of speed, capacity, quality of the multi-integration and to enhance the effectiveness, is currently the focus of attention of the market. PCI Express (PCIe) is considered to provide higher bandwidth, the future will be widely used in Desktop, Mobile, Server, replacing the traditional areas such as the latest PCI interface. Unlike the PCI Bus number to download (Multi-Drop) parallel bus technology PCI Express switching (Switch) end-to-end (Peer-to-Peer) the serial transmission technologies.PCI Express in transmission data of physical layer is by a group single workers channel (Lane) composed sent end (Tx) and receives end (Rx), each group PCI Express are can independent using themselves of channel and South Bridge chip contact, no longer is take shared bus of schema; which PCI Express different Yu PCI will bandwidth distribution to Bus Shang all equipment using, but for host system in the of each a slot provides dedicated of bandwidth, Not only eliminating data transfer interference problems, and each data has priority privilege, so transfer for PCI Express architecture is faster than traditional PCI Bus. Early PCI Express version before a single channel (Lane) transfer speeds of up to 250MB/s,PCI Express X2 unidirectional and bi-directional maximum bandwidth 500MB and 1000MB/sec respectively. Current PCI Express bandwidth of each channel is 2.5Gbps and maintain backward compatibility with legacy PCI software is higher than most other Bus efficiency on the market. In addition, the match may at any time modify the Scalability characteristics of the Bus width, make PCI Express X1, X2, X4, x8, x12, x16 and flexible Bus width choices, which have different foot block design, is to tie in with the future applications of multimedia and high-speed transmission.PCI Express x16, for example, transfer bandwidth up to 4GB/s, more than AGP 8X 2.1GB/se nearly 1 time, is enough to replace them. （4）OCB（On-Chip Bus） When the IC system design into a single chip (System-on-a-Chip;SoC) after the era of design, a large number of Silicon intellectual wealth (SIP;Silicon Intellectual Property) can be highly integrated into a single chip. Design of single-chip system one of the major difficulties is the mutual communication between the modules. On-chip bus solution is development (On-Chip Bus;OCB) interface specifications, take in single-chip system, connect the module corner. OCB form IP integration in SoC phase one of the indispensable key technical standards. SoC highly consolidated trend means that more IP core being connected on the OCB, who is more the bus master (Bus Master) on IP connects to the OCB. Due to competition among Bus Master Bus use derive substantial right to use Bus conversion costs, there are multiple Bus Master interleaves, cause the Bus to use less efficient,Makes engaged in SoC research related industry who due to cannot real-time gets Bus right and led to single chip system integration failed; or SoC development early on be decided OCB related design parameter as operation frequency, and Bus transmission data width and the Bus class, details, makes SoC detail early design often sharply back and forth change system schema so delay development Shi thread of problem; plus for ensure each connection to OCB Shang of IP are can comply with established of Bus agreement, Avoid flawed interface IP designed to endanger the entire OCB normal operation of the system, all these factors are all sectors of the IT industry official research, begin to envisage common specifications should facilitate the emergence of SoC Bus standards. VSIA (Virtual Socket Interface Alliance) for the OCB envisages development of a common framework specification, but SoC Bus standards battle is currently enjoying a status. For example IBM processor local bus is a bus belonging to the hierarchical structure, which contains the processor local bus (PLB), on-chip peripheral bus (OPB), PLB, OPB arbitration the arbitration and the PLB to OPB bridge; also Core-Connect with IBM, Motorola IP-bus under M-Core Methodology, and ARM AMBA (Advanced Microcontroller Bus Architecture), Altera Avalon, as well as VSIA VSIA On-Chip Bus, and so on.If these bus specifications fees, is to have the authority, almost impossible to free free to use, so there is still a promotional limited. Opencores (to promote IP based on the concept of Open Source programming organization) recommended SoC Bus are Silicore Corporation developed the Wishbone bus specifications on the chip without authorization, which is also free and open, it was welcomed by the SoC design.