Silicon Labs introduced the industry’s most highly integrated clock IC for wireless infrastructure applications including small cell and macro cell base stations. Silicon Labs’ new Si5380 clock generator is the industry’s first clock IC capable of replacing a low phase noise integer-N clock, voltage-controlled crystal oscillator (VCXO), discrete loop filters and voltage regulator components with one single-chip device.
The Si5380 clock provides comparable phase noise performance to discrete conventional solutions while delivering breakthrough advancements in solution footprint, bill of materials (BOM) cost, power consumption, performance and ease of use.
Silicon Labs’ new Si5380 clock is the industry’s first single-chip wireless clock IC optimized for size, power, integration and performance, making it an ideal fit for small cell applications.
The Si5380 clock leverages Silicon Labs’ latest fourth-generation DSPLL technology to provide a purpose-built solution optimized for next-generation small cells and macro cell remote radio head (RRH) designs. DSPLL technology’s innovative dual-loop mixed-signal architecture integrates a single high-performance 15 GHz analog voltage-controlled oscillator within a digital phase-locked-loop (PLL) architecture that eliminates the need for discrete loop filters and low-drop-out (LDO) regulators. The resulting clock solution provides an optimal combination of ultra-low phase noise clock synthesis with best-in-class PLL integration.
The Si5380 clock has a 66 percent smaller printed circuit board (PCB) footprint and 30 percent lower power consumption than competing VCXO-based clock IC solutions. Power-efficient timing components are especially important for today’s small cells, which have limited power budgets and often are powered using Power over Ethernet (PoE) technology. Given that the DSPLL integrates all PLL and power supply regulation elements on-chip, the Si5380 device delivers high board-level noise immunity, integrated power supply noise rejection and consistent, repeatable phase noise performance across temperature.
While VCXO-based clock solutions often suffer from degraded spurious performance when subjected to vibration, the Si5380 device’s integrated DSPLL technology provides excellent spurious response regardless of the system environment. Furthermore, the Si5380 clock guarantees low phase noise operation when locked to a high jitter input clock, ensuring that data converter performance is not degraded by external effects. The Si5380 generates 4G/LTE frequencies up to 1.47456 GHz and provides up to 12 independently configurable clocks, which can be used for clocking JESD204B-compliant data converters, FPGAs and other logic devices.
