imec has signed a strategic partnership with ARM. ARM’s involvement with imec’s INSITE program will focus on addressing the impacts of circuit design and system-level architecture on power, performance, area and cost of nanotechnology chip process nodes from 7nm and beyond.
“This strategic collaboration with ARM is extremely important for imec,” stated Luc Van den hove, president and CEO at imec. “Collaborating with ARM enables our partners to leverage imec’s process developments to accelerate their design cycle and shorten their time-to-market.”
“Advanced process nodes are vital in driving performance and efficiency and our collaboration with imec will push the boundaries of what consumers can expect,” said Simon Segars, chief executive officer, ARM.
“Optimizing advanced nanotechnology nodes is highly complex and it needs focused expertise to meet challenges in areas such as patterning and power. Our collaboration delivers a breadth of talent, with imec’s experience in advanced logic, circuit and system design, ARM’s leadership in IP design for advanced CMOS technologies and support from across the well-established imec ecosystem.”
A variety of process options can be used to define a technology node, such as the type and number of lithography exposures, the device architecture such as FinFETs or lateral nanowires, the local interconnect scheme, cell architecture and the metallization scheme.
Increasingly, optimizing the many choices requires detailed assessment of their interactions with the designs and applications which will utilize the technology.
Initiated in 2009 and now with more than ten international partners, INSITE consolidates the technology knowledge of imec’s logic device scaling program to help companies anticipate new technologies when designing next-generation systems and applications.
Studying process assumptions, design targets and trade-offs with expected system performance scaling, INSITE enables strategic product roadmap steering, early feedback toward technology specification, and early decisions on required architectural design changes. This knowledge enables faster learning cycles for technology adoption with reduced risks.
